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White Electronic Designs
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
Access Times of 15*, 17, 20, 25, 35, 45, 55ns Battery Back-up Operation * 2V Data Retention (EDI88130LPS) CS1#, CS2 & OE# Functions for Bus Control Inputs and Outputs Directly TTL Compatible Organized as 128Kx8 Commercial, Industrial and Military Temperature Ranges Thru-hole and Surface Mount Packages JEDEC Pinout * 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102) * 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9) * 32 lead Ceramic SOJ (Package 140) * 32 pad Ceramic Quad LCC (Package 12) * 32 pad Ceramic LCC (Package 141) * 32 lead Ceramic Flatpack (Package 142)
EDI88130CS
Single +5V (10%) Supply OperationThe EDI88130CS is a high speed, high performance, 128Kx8 bits monolithic Static RAM. An additional chip enable line provides system memory security during power down in non-battery backed up systems and memory banking in high speed battery backed systems where large multiple pages of memory are required. The EDI88130CS has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. A low power version, EDI88130LPS, offers a 2V data retention function for battery back-up applications. Military product is available compliant to MIL-PRF38535.
* 15ns access time is advanced information, contact factory for availability.
FIGURE 1 - PIN CONFIGURATION 32 DIP 32 SOJ 32 CLCC 32 FLATPACK TOP VIEW
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2# WE# A13 A8 A9 A11 OE# A10 CS1# I/O7 I/O6 I/O5 I/O4 I/O3
32 QUAD LCC TOP VIEW
A12 A14 A16 NC VCC A15 CS2
PIN DESCRIPTION
I/O0-7 A0-16 WE# CS1#, CS2 OE# VCC VSS NC Data Input/Output Address Inputs Write Enable Chip Select Output Enable Power Supply Ground Not Connected
4
3
2
1
32
31
30
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20
29 28 27 26 25 24 23 22 21
WE# A13 A8 A9 A11 OE# A10 CS1# I/O7
Block Diagram
Memory Array
I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6
A0-16
Address Buffer
Address Decoder
I/O Circuits
I/O0-7
WE# CS1# CS2 OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Industrial Military Storage Temperature, Ceramic Power Dissipation Output Current Junction Temperature, TJ -0.2 to 7.0 -40 to +85 -55 to +125 -65 to +150 1.7 40 175 Unit V C C C W mA C OE# CS1# CS2 X H X X X L H L H L L H X L H
EDI88130CS
TRUTH TABLE
WE# Mode X Standby X Standby H Output Deselect H Read L Write Output High Z High Z High Z Data Out Data In Power Icc2, Icc3 Icc2, Icc3 Icc1 Icc1 Icc1
CAPACITANCE
TA = +25C Max Parameter Address Lines Data Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz LCC 6 8
CSOJ,DIP, Flatpack
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Unit pF pF
12 14
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5 Typ 5.0 0 -- -- Max 5.5 0 VCC +0.5 +0.8 Unit V V V V
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
VCC = 5.0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol ILI ILO Icc1 Icc2 Icc3 VOL VOH Conditions VIN = 0V to VCC VI/O = 0V to VCC WE#, CS1# = VIL, II/O = 0mA, CS2 = VIH CS1# VIH and/or CS2 VIL, VIN VIH or VIL CS1# VCC -0.2V and/or CS2 0.2V VIN VCC -0.2V or VIN 0.2V IOL = 8.0mA IOH = -4.0mA (15-17ns) (20ns) (25-55ns) (17-55ns) (15ns) CS (17-55ns) CS (15ns) LPS Min -- -- -- -- -- -- -- -- -- -- -- 2.4 Typ -- -- Max 5 10 300 225 200 25 60 10 15 5 0.4 -- Units A A mA mA mA mA mA mA mA mA V V
3 -- -- -- --
AC Test Conditions
Figure 1
Vcc
Figure 2
480
Vcc
Input Pulse Levels
480
VSS to 3.0V 5ns 1.5V Figure 1
Q
255 30pF
Q
255 5pF
Input Rise and Fall Times Input and Output Timing Levels Output Load
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC CHARACTERISTICS - READ CYCLE (15 to 20ns)
VCC = 5.0V, Vss = 0V, -55C TA +125C 15ns* Alt. tRC tAA tACS tACS tCLZ tCLZ tCHZ tCHZ tOH tOE tOLZ tOHZ tPU tPU tPD tPD Min 15 Max 15 15 15 5 5 6 6 3 6 0 5 0 0 15 15 0 0 17 17 0 6 0 0 3 6 0 5 5 7 7 3 Min 17 Symbol Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in Low Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) JEDEC tAVAV tAVQV tE1LQV tE2HQV tE1LQX tE2HQX tE1HQZ tE2LQZ tAVQX tGLQV tGLQX tGHQZ tE1LICCH tE2HICCH tE1HICCL tE2LICCL 17ns Max 17 17 17 5 5
EDI88130CS
20ns Min 20 Max 20 20 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8 8 7 8
20 20
1. This parameter is guaranteed by design but not tested. * 15ns access time is advanced information, contact factory for availability.
AC CHARACTERISTICS - READ CYCLE (25 to 55ns)
VCC = 5.0V, Vss = 0V, -55C TA +125C Symbol Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in Low Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1)
1. This parameter is guaranteed by design but not tested.
25ns Alt. tRC tAA tACS tACS tCLZ tCLZ tCHZ tCHZ tOH tOE tOLZ tOHZ tPU tPU tPD tPD Min 25 Max 25 25 25 5 5 10 10 0 10 0 10 0 0 25 25 0 0 0 0 5 5 Min 35
35ns Max 35 35 35 5 5 15 15 0 15 0 15 0 0 35 35 Min 45
45ns Max 45 45 45 5 5 20 20 0 20 0 20 0 0 45 45 Min 55
55ns Max 55 55 55 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
JEDEC tAVAV tAVQV tE1LQV tE2HQV tE1LQX tE2HQX tE1HQZ tE2LQZ tAVQX tGLQV tGLQX tGHQZ tE1LICCH tE2HICCH tE1HICCL tE2LICCL
20 20 25 20
55 55
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC CHARACTERISTICS - WRITE CYCLE (15 to 20ns)
VCC = 5.0V, Vss = 0V, -55C TA +125C 15ns* Min 15 12 12 12 12 0 0 0 12 12 12 12 0 0 0 0 0 0 0 7 7 7 3 Max Min 17 13 13 13 13 0 0 0 13 13 13 13 0 0 0 0 0 0 0 8 8 8 3 Symbol JEDEC Alt. tWC tAVAV tE1LWH tCW tE1LE1H tCW tE2HWH tCW tE2HE2L tCW tAVWL tAS tAVE1L tAS tAVE2H tAS tAW tAVWH tWLWH tWP tWLE1H tWP tWLE2L tWP tWHAX tWR tE1HAX tWR tE2LAX tWR tWHDX tDH tE1HDX tDH tE2LDX tDH tWHZ tWLQZ tDVWH tDW tDVE1H tDW tDVE2L tDW tWHQX tWLZ 17ns Max
EDI88130CS
20ns Min 20 15 15 15 15 0 0 0 15 15 15 15 0 0 0 0 0 0 0 10 10 10 3 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Write Cycle Time Chip Enable to End of Write
Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
7
8
8
AC CHARACTERISTICS - WRITE CYCLE (25 to 55ns)
VCC = 5.0V, Vss = 0V, -55C TA +125C Min 25 20 16 16 0 0 0 20 20 20 20 20 0 0 0 0 0 0 0 15 15 15 3 0 0 0 25 25 30 30 30 0 0 0 0 0 0 0 20 20 20 3 25ns Max Min 35 25 20 20 0 0 0 35 35 30 30 30 5 5 5 0 0 0 0 20 20 20 3 Symbol JEDEC Alt. tWC tAVAV tE1LWH tCW tE1LE1H tCW tE2HWH tCW tE2HE2L tCW tAVWL tAS tAVE1L tAS tAVE2H tAS tAVWH tAW tAVEH tAW tWLWH tWP tWLE1H tWP tWLE2L tWP tWR tWHAX tE1HAX tWR tE2LAX tWR tWHDX tDH tE1HDX tDH tE2LDX tDH tWLQZ tWHZ tDW tDVWH tDVE1H tDW tDVE2L tDW tWHQX tWLZ 35ns Max 45ns Max 55ns Max
Parameter Write Cycle Time Chip Enable to End of Write
Min 45 35 25
Min 55 45 40
16
20
25 25 0 0 0 45 45 35 35 35 5 5 5 0 0 0 0 25 25 25 3
40 40
Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
10
13
15
20
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIGURE 2 - TIMING WAVEFORM - READ CYCLES
tAVAV
ADDRESS
EDI88130CS
tAVQV
CS1#
tAVAV
ADDRESS
Icc
ADDRESS 1 ADDRESS 2
tE1LQV tE1LQX tE1LICCH tE2HQV
CS2
tE1HQZ tE1HICCL tE2LICCL
tAVQV
DATA I/O
tAVQX
DATA 1 DATA 2
tE2HICCH tE2HQX
OE#
tGLQV tGLQX
DATA I/O
tGHQZ
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (CS1# AND/OR CS2 CONTROLLED, WE# HIGH)
FIGURE 3 - WRITE CYCLE 1
tAVAV
ADDRESS
tAVWL
WE#
tAVWH tWLWH
tWHAX
tE1LWH
CS1#
CS2
tE2HWH
tDVWH
tWHDX
DATA IN
tWLQZ
DATA OUT
tWHQX
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
FIGURE 4 - WRITE CYCLES 2
tAVAV
ADDRESS ADDRESS
WRITE CYCLES 3
tAVAV tAVE2H
WE#
tAVE1L
WE#
tE1LE1H
tE1HAX
tE2HE2L
tE2LAX
CS1#
CS1#
CS2
CS2
tDVE1H
DATA I/O
tE1HDX
DATA I/O
tDVE2L
tE2LDX
WRITE CYCLE 2 - EARLY WRITE, CS1# CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
DATA RETENTION CHARACTERISTICS (EDI88130LPS Only)
-55C TA +125C Conditions VCC = 2.0V CS1# VCC -0.2V and/or CS2 VSS +0.2V VIN VCC -0.2V or VIN 0.2V Characteristic Low Power Version only Data Retention Voltage Data Retention Quiescent Current Chip Disable to Data Retention Time (1) Operation Recovery Time (1)
NOTE: 1. Parameter guaranteed by design, but not tested. * Read Cycle Time
EDI88130CS
Sym VCC ICCDR TCDR TR
Min 2 - 0 Tavav*
Typ - 0.5 - -
Max - 2 - -
Units V mA ns ns
FIGURE 5 - DATA RETENTION - CS1# CONTROLLED
Data Retention Mode
Vcc
4.5V VCC 4.5V
tCDR
CS1#
CS1# VCC -0.2V
tR
DATA RETENTION, CS1# CONTROLLED
FIGURE 6 - DATA RETENTION - CS2 CONTROLLED
Data Retention Mode
Vcc
4.5V VCC 4.5V
tCDR
CS2
CS2 0.2V
tR
DATA RETENTION, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE 12: 32 PIN CERAMIC QUAD LCC
0.120 0.060 0.028 0.022 0.020 X 45 REF.
EDI88130CS
0.050 BSC. 0.560 0.540
0.458 0.442
0.055 0.045
0.040 X 45 REF.
ALL DIMENSIONS ARE IN INCHES
PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600 MILS WIDE)
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.620 0.600
0.100 TYP
0.155 0.115
0.600 NOM
ALL DIMENSIONS ARE IN INCHES
PACKAGE 102: 32 PIN SIDEBRAZED CERAMIC DIP (400 MILS WIDE)
1.616 1.584
Pin 1 Indicator 0.200 0.125 0.061 0.017 0.020 0.016 15 x 0.100 = 1.500
0.060 0.040
0.420 0.400
0.100 TYP
0.155 0.115
0.400 NOM
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE 140: 32 LEAD CERAMIC SOJ
0.108 0.088
EDI88130CS
0.840 0.820 0.040 0.030 0.050 TYP
0.440 0.430
0.155 0.120
0.379 REF
ALL DIMENSIONS ARE IN INCHES
PACKAGE 141: 32 PAD CERAMIC LCC
0.096 0.080 0.028 0.022 0.840 0.820
0.405 0.395
ALL DIMENSIONS ARE IN INCHES
0.050 TYP
PACKAGE 142: 32 PIN CERAMIC FLATPACK
0.830 0.810 0.007 0.003 0.370 0.250 1.00 REF 0.290 0.270 0.040 0.030 0.019 0.015 0.116 0.100
0.420 0.400
Pin 1
0.045 0.020
0.050 TYP
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION
EDI88130CS
EDI 8 8 130 CS X X X
WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 128Kx8 (130 = Dual CS) TECHNOLOGY: CS = CMOS Standard Power (5V) LPS = Low Power ACCESS TIME (ns) PACKAGE TYPE: C = 32 lead Sidebrazed DIP, 600 mil (Package 9) F = 32 lead Ceramic Flatpack (Package 142) L = 32 pad Ceramic LCC (Package 141) L32 = 32 pad Ceramic Quad LCC (Package 12) N = 32 lead Ceramic SOJ (Package 140) T = 32 lead Sidebrazed DIP, 400 mil (Package 102) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened I = Industrial C = Commercial
-55C to +125C -40C to +85C 0C to +70C
White Electronic Designs Corp. reserves the right to change products or specifications without notice. March 2002 Rev. 11 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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